This invention relates to semiconductor memory devices and more particularly to an improved high-density MOS random access, dynamic read/write memory.
The most widely used semiconductor memory device for computers is the MOS dynamic RAM, such as the 64K-bit device illustrated in U.S. Pat. No. 4,239,993, issued to McAlexander, White and Rao, assigned to Texas Instruments. These devices have traditionally included a "page mode" of operation in which the row address strobe RAS is held low while the column address strobe CAS is toggled, producing faster data output for data located in the same page (same row address but different column address). Now devices are being manufactured having a "nibble mode" of operation in which the RAS and CAS sequence is the same as page mode, but, instead of latching in a new column address each time CAS is toggled, the original column address is used and incremented by 1. Nibble mode is faster, but limited in address range. From a manufacturer's standpoint, production of both page mode and nibble mode devices requires processing two different types of slices, which adds to the cost of both. It is of course preferable to produce a very large quantity of one design, rather than a number of different designs.
Dynamic RAM chips providing either page mode or nibble mode have been described by Shimotori et al, ISSCC Digest of Technical Papers, p. 228, Feb. 1983, but the the selection is made by using different timing inputs, which placed a burden on the system designer.
It is the principal object of this invention to provide improved dynamic random access memory devices, particularly for providing either page mode or nibble mode. Another object is to provide selection between page mode and nibble mode for semiconductor dynamic memory devices which use a low cost manufacturing method, and/or which do not restrict the system designer.